Many electronic devices formed on a substrate are dual-gate or dual-port devices. One example of a dual-gate or dual-port electronic device is a Voltage-Variable Capacitor (VVC) cell. VVC cells are commonly used in Voltage-Controlled Oscillators (VCOs) to generate an oscillation frequency for establishing communications, such as in cellular communications. The efficiency of these VCOs may be determined by a quality, or “Q”, factor and a tuning range. The Q factor is a measure of the amount of energy being stored and dissipated by the VCO, and the tuning range establishes a bandwidth of operation for the VCO based on the oscillation frequency. A higher Q factor and greater tuning range indicate a greater efficiency of the VCO.
A significant portion of the energy dissipated by a VCO may be attributed to energy dissipated across resistances in the VCO. One source of parasitic resistance contributing to energy dissipation may be found in the VVC cells. VVC cells include polysilicon gates or fingers that are typically formed on a substrate (e.g., in an Integrated Circuit (IC)) having channel regions formed therein, where the polysilicon gates are coupled together by metal interconnects. The metal interconnects, the polysilicon gates, the channel regions, and the substrate may each have a corresponding parasitic resistance that contributes to energy dissipation in the VCO.
One VVC cell configuration is a dual-gate VVC cell that is operated differentially to minimize the parasitic resistance contributed by the substrate. The dual-gate VVC cell includes interdigitated sets of polysilicon fingers (e.g., a first set of polysilicon fingers interdigitated with a second set of polysilicon fingers), and each set of polysilicon fingers is coupled together by a different metal interconnect. In conventional VVC cell arrays, one set of polysilicon fingers for each of the VVC cells are connected together by a first set of metal interconnects, and the other set of polysilicon fingers for each of the VVC cells are connected together by a second set of metal interconnects. The metal interconnects in the VVC have a significant parasitic resistance similar in magnitude to the parasitic resistances associated with the polysilicon fingers and substrate.
Accordingly, an interconnect configuration for a dual-gate or dual-port electronic device that minimizes parasitic resistance is desired. More specifically, an interconnect configuration for a VVC cell array that minimizes parasitic resistance is desired. In addition, a method for routing interconnects in a dual-gate or dual-port electronic device that minimizes parasitic resistance is desired. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description of the embodiments and the appended claims, taken in conjunction with the accompanying drawings and this background.